A novel method of graded junction termination extension (JTE) formation for high-voltage 4H-SiC power devices is presented. Unlike conventional multiimplantation or tapered thickness mask approaches utilizing several photolithography steps, the new termination technique utilizes a single mask with window areas varied laterally away from the main junction, a single-step boron implantation, and drive-in diffusion at elevated temperature. Numerical device simulations have been performed for the initial JTE structure and mask optimization. 4H-SiC p-i-n rectifiers with an active area of 1 mm × 1 mm were fabricated and characterized. The fabricated devices exhibited 2.5-kV blocking voltage, which is close to the theoretical value of an ideal parallel-plane p-n junction.
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Bolotnikov et al. (2010) studied this question.
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