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A new high-gain, wideband Si monolithic amplifier utilising a new parallel feedback and adjustable peaking technique has been developed using a high-speed Si bipolar process technology. An objective of the design was to enhance gain and bandwidth performance by preventing parasitic oscillation. This IC achieves a wide bandwidth of DC-3.5 GHz, and a high gain of 30 dB. Furthermore, a noise level of 5 dB at 1 GHz and a total power dissipation of 180 mW at a power supply voltage of 6 V were attained.
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Ishihara et al. (1989) studied this question.
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