What does this research mean for the field?

An event-driven, clock-gated security architecture utilizing anomaly detection and a lightweight block cipher provides effective cryptographic protection for resource-constrained FPGA edge devices while significantly improving dynamic power efficiency. Novelty: ClaimNovelty.METHODOLOGICAL. Consensus alignment: ConsensusAlignment.NEUTRAL.

What question did this study set out to answer?

To develop a low-power, adaptive FPGA security architecture that activates encryption only when anomalous input data is detected.

September 5, 2026Ain Shams Engineering JournalOpen Access

Design and implementation of a dynamic power-aware secure processing architecture on FPGA using VERILOG HDL

View Full Paper

Ask AI

Bookmark

Authors

HMHardik ModiCharotar University of Science and Technology TSTaoufik SaidaniNorthern Border University MMMayur MakwanaCharotar University of Science and Technology

Discussion

Member takes

Implication

Hardware evaluation demonstrates event-driven cipher activation on a Spartan-6 FPGA, highlighting improved dynamic power efficiency for resource-constrained edge devices.

Key Points

To develop a low-power, adaptive FPGA security architecture that activates encryption only when anomalous input data is detected.
Designed an event-driven hardware pipeline using Verilog HDL integrating a 4-tap symmetric FIR filter and an anomaly detection unit.
Controlled clock distribution to a 16-bit PRESENT lightweight block cipher using a BUFGCE integrated clock-gating cell based on filter threshold triggers.
Synthesized and targeted the architecture on a Xilinx Spartan-6 FPGA operating at a clock frequency of 50 MHz.
Implemented hardware consumed compact logic resources totaling 62 look-up tables (LUTs) and 64 flip-flops.
Clock gating successfully disabled dynamic clock routing to the cryptographic core during normal input conditions, reducing switching activity.

Cite This Study

Modi et al. (2026) studied this question.

synapsesocial.com/papers/6a9bd3a66b95aff0620eada8 https://doi.org/10.1016/j.asej.2026.104412

View Full Paper

Ask AI

Bookmark

Implication

Hardware evaluation demonstrates event-driven cipher activation on a Spartan-6 FPGA, highlighting improved dynamic power efficiency for resource-constrained edge devices.

Design and implementation of a dynamic power-aware secure processing architecture on FPGA using VERILOG HDL

Discussion

Member takes

Implication

Key Points

Cite This Study

Design and implementation of a dynamic power-aware secure processing architecture on FPGA using VERILOG HDL

Discussion

Member takes

Implication

Key Points

Cite This Study

Also Consider

Also Consider