A nonoverlapping gate charge-coupling technology for serial memory and signal processing applications

Of the many technologies available to implement efficient and stable charge-coupled devices (CCD's), most employ a multilevel metal, overlapping gate approach. As a consequence, the CCD process becomes generally more complex and the resulting overlap capacitance can be embarrassing for serial memory applications. This paper describes a single level aluminium gate process, the notable features of which are simplicity, extremely high yield, low interphase capacitance, and very high packing density. Interelectrode spacings in the range 2000 /spl Aring/-5000 /spl Aring/ are achieved. The performance capability is described in the context of an analog delay line.