A digital common-mode rejection technique for differential analog-to-digital conversion

A multibit /spl Delta//spl Sigma/ analog-to-digital converter can achieve high resolution with a lower order /spl Delta//spl Sigma/ modulator and lower oversampling ratio than a single-bit design, but it requires a multibit internal flash analog-to-digital converter rather than a simple comparator. In an implementation with a fully differential analog front end, the flash analog-to-digital converter must quantize a differential voltage relative to a set of differential reference voltages. Though analog techniques for differential analog-to-digital conversion exist, implementing them in a low-voltage single-poly CMOS process is a challenging circuit design problem. This paper presents a digital common-mode rejection technique for differential analog-to-digital conversion (ADC), which avoids the circuit complexity and die area requirements of analog common-mode rejection techniques. This technique was used to implement the internal quantizer in two high-performance single-poly CMOS ADC /spl Delta//spl Sigma/ modulator prototypes with over 98-dB peak signal-to-noise-and-distortion ratio and 105-dB spurious-free dynamic range. Implementation details, die area requirements, and measured common-mode rejection are presented for the prototype. Signal-processing details of digital common-mode rejection within the /spl Delta//spl Sigma/ modulator are presented, showing that injected common-mode noise results only in modulation of the quantization error power and does not create spurious tones.