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In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at 2f0and 3f0frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25-μm GaAs pHEMT technology with VDD of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16 transistors in parallel to provide 39-40-dBm output power. The class-F HPA achieves a 10-W output power and a peak power added efficiency (PAE) of 63% for pulsed-mode operation with a pulse repetition frequency (PRF) of 1 kHz and a duty cycle of 10%. The measured peak output power and PAE in the continuous-wave (CW) operation are 9.3 W and 58%, respectively.
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Alizadeh et al. (2020) studied this question.
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