Novel process for widening memory window of sub-200 nm ferroelectric-gate field-effect transistor by ferroelectric coating the gate-stack sidewall

Ferroelectric-gate field-effect transistors (FeFETs) with metallurgical-gate lengths of 140 nm, 160 nm and 190 nm were successfully fabricated using a novel fabrication process. The gate stacks of the FeFETs were Pt/Sr 0.8 Ca 0.2 Bi 2 Ta 2 O 9 (SCBT)/HfO 2 /Si. Key to the process was covering the as-etched gate-stack sidewalls with SCBT precursor films and annealing altogether. The FeFETs which underwent the novel process showed larger memory windows than those without the process by about 0.5 V at scanned gate-voltages of 1 ± 5 V. Endurances of the FeFETs made by the novel process were measured up to 10 9 cycles with good separations of the on- and off-states. The endurance pulses were 1 ± 5 V with 2 μ s period. Good data-retentions of them were also demonstrated which were measured for at least 6.5 days.