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In this work, we demonstrate that P-MOSFETs integrated on SOI (23-nm Si–25-nm BOX) are not immune to floating body effects. These transistors operate as dynamically depleted (DD) devices, meaning that they are fully depleted at low drain bias and partially depleted at higher biases. Since the devices are processed without body contact and the Si film is moderately thick, the floating area is smaller compared to partially depleted MOSFETs, which makes the transient characterization of the FB effects challenging. The first part of this article deals with the FB effects sensitivity to the drain bias, the channel doping, the gate width, the Si-channel thickness, and the back-gate bias through static measurements and TCAD simulations. The second part proposes for the first time an extraction of the floating area charging and discharging time constants and their dependence on the previously mentioned parameters. The final part presents, by means of both measurements and TCAD, an estimation of the carriers lifetime in the analyzed devices.
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Boutayeb et al. (2025) studied this question.
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