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Capacitance–voltage (C–V) characteristics of the metal-ferroelectrics-insulator-silicon (MFIS) structure have been calculated by the conventional metal-oxide-silicon (MOS) analysis method. The potential profile is obtained by using the Poisson equation of D–E hysteresis, and its capacitance is estimated as combination of SiO2-Si capacitance and ferroelectric film capacitance obtained from dielectric constant corresponding to the internal field. PbZrxTi1-x O3 (PZT) and SrBi2Ta2O9 (SBT) ferroelectrics, SiO2, MgO, SrTiO3 (STO) and CeO2 insulators, and silicon semiconductor, were used as independent parameters for the analyses. The dependence of MFIS C–V characteristics on ferroelectric properties, film thickness and impurity concentration of the semiconductor is calculated. Film thicknesses of ferroelectrics and insulators affect the memory window width markedly, and have to be optimized in order to obtain a large memory window width. On the other hand, MFIS C–V characteristics and memory window width are not influenced by P r because the effective P r is small in the MFIS structure.
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Kanashima et al. (1999) studied this question.
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