Experimental study demonstrates gate-tunable random telegraph noise in silicon-on-insulator transistors, indicating a scalable pathway for room-temperature CMOS probabilistic accelerators.
Key Points
To develop a CMOS-compatible probabilistic bit that harnesses intrinsic random telegraph noise under direct gate-voltage control for energy-efficient probabilistic computing.
Characterized intrinsic random telegraph noise (RTN) in fully depleted silicon-on-insulator field-effect transistors under varying gate voltages.
Evaluated capture and emission dynamics, dwell-time statistics, and pairwise independence across independent RTN streams using cross-correlation and probabilistic Boolean logic.
Emulated simulated annealing on a two-dimensional hydrophobic-polar protein-folding benchmark and mapped the algorithm into a digital lookup-table architecture.
RTN dynamics adhered to Shockley-Read-Hall kinetics with Poisson-distributed dwell times, producing a tunable sigmoid bias-to-probability transfer response.
Cross-correlation and probabilistic logic operations verified pairwise statistical independence between separate transistor noise channels.
Simulated annealing reached optimal low-energy protein-folding states in fewer stochastic update iterations than required by exhaustive candidate enumeration.