Design and implementation of quaternary NMOS integrated circuits for pipelined image processing

A pattern-matching procedure for performing four-valued image processing based on cellular logic operation is proposed, allowing two different templates to be processed simultaneously in a pipelined manner. Based on these double pattern-matching cells, a compact NMOS image-processing chip has been implemented. It is demonstrated that the compactness comes from reduced interconnections in the double pattern-matching cells using a quaternary multiplexer or T gates, realized with pass transistors and multiple ion implants.