Josephson 32-bit shift register

A 32-b shift register designed by edge-triggered gates was tested with +or-25% bias margin and +or-81% input margin for the full array. Simulations showed +or-55% bias margin at 3.3 GHz and worked up to a maximum frequency of 30 GHz with a junction current density of 2000 A/cm/sup 2/, although the shift register has only been tested up to 500 MHz, limited by instrumentation. This edge-triggered gate, consisting of a pair of conventional Josephson logic gates in series, has the advantages of wide margins, short reset time, and insensitivity to global parameter variations.