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An oxide isolated Integrated Schottky Logic (ISL) gate has been designed and fabricated using 1.25 µm minimum goemetries and a 1 µm thick epitaxy layer. Computer simulations and experimental results show good agreement and demonstrate that this gate structure provides a room temperative gate delay of approximately 0.7ns at a current level of 100 µA.
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Roberts et al. (1981) studied this question.
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