CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops

The recycling integrator correlator (RIC) is a novel approach for implementing correlators that consumes less power than conventional digital or analog CMOS correlators. The RIC modulates the product of a received signal and a pseudorandom noise (PN) sequence into a bit stream by first-order /spl Delta//spl Sigma/ modulation. The accumulated number represents the quantized correlation value. Using RICs, two functional blocks of a direct sequence code division multiple access (DS-CDMA) demodulator targeting IMT-2000, a matched filter (MF) and a delay locked-loop (DLL) are implemented in silicon. In the fabricated 256-tap QPSK MF-RIC, two 256-tap double-sampling MFs sample the I and Q received analog signals at a rate of 8 Msample/s. Their outputs are 9-bit quantized correlation values with a 256-chip PN sequence at the same rate as the sampling rate. The DLL-RIC can adapt to spreading ratios from 32 to 256 with the use of an auxiliary ADC that can compensate the degradation of dynamic range when the spreading ratio is small. Processed in a 0.35-/spl mu/m CMOS process, the MF-RIC and the DLL-RIC, respectively, occupy 22.8 and 2.28 mm/sup 2/ and dissipate 23.0 and 3.4 mW at 2-V power supply.