A Novel Symmetrical Rectifier Configuration With Low Voltage Stress and Ultralow Output-Current Ripple

The dc–dc topologies with capacitive output filter are going to be widely used especially for high-output current applications because of its inherent advantages in the lower voltage stress on rectifiers and the smaller occupied printed circuit board layout area at the secondary side. However, the parasitic resonance between the equivalent leakage inductance of the power transformer and the equivalent output junction capacitance of the rectifier still practically exists in the center-tapped rectification configuration, which leads to considerable voltage ringing on the rectifier and then results in the utilization of the rectifier with much higher breakdown voltage rate and the decrease of conversion efficiency. Moreover, the relatively larger output-current ripple induces the both larger conduction loss in the secondary-side windings of the power transformer and the capacitive output filter. In this paper, a novel symmetrical rectifier configuration is proposed, which can effectively clamp the practical voltage stress on the rectifier without any parasitical voltage spike and reduce the output-current ripple due to the bypass effect of the auxiliary flying-balancing capacitors. The leakage inductance and the output filter capacitor can be treated as an inherent smallLCfilter to reduce the output voltage ripple further. Based on the theoretical analysis and the optimal design considerations, a 300-W lab-madeLLCresonant dc–dc converter with this proposed configuration is built up to verify its advantages in high conversion efficiency.