An Adaptive-Resolution SAR ADC With Metastability-Sensing 1-bit TDC in 65-nm CMOS

We propose a metastability-sensing one-bit time-to-digital converter (TDC) for a successive-approximation (SAR) analog-to-digital converter (ADC) that detects a metastability-specific current in the comparator, gates its clock to stop the conversion cycle, and outputs partially resolved sub-resolution code. This approach improves the power efficiency by reducing the logic overhead and minimizing the TDC activation time. The SAR operates in the adaptive-resolution mode, using dual-rail asynchronous logic to track unresolved bits and a single-gate most significant bit (MSB) inversion to correct errors. A 7-bit capacitive digital-to-analog converter (CDAC) combined with an 8-bit SAR core generates 511 sub-resolution codes. Fabricated in 65 nm CMOS, the prototype achieves a peak SNDR of 50.6 dB at 40 MS/s, ENOB=8.16/8.11 at 1 MHz/20 MHz, and 40.9~μ W total power (0.7 V digital/0.8 V analog), yielding a Walden figure-of-merit (FoM) of 3.7~fJ/conv.\,step in 0.004 mm2 active area. A static-current condition in the fabricated prototype’s TDC/comparator interface incurs excess analog power in the measured results; proposed circuit modifications are projected by simulation to eliminate this overhead.