Neuristor propagation in low impedance line†

This paper describes the character of neuristor operation composed of a lumped parameter delay line with a negative resistance element parallel to the capacitance, as a function of the precise character of the negative resistance element. This model allows a neuristor pulse transmission in cases with. very low characteristic impedance Z0 = √(L/C). The experiments cover a Z0 value down to 11 Ω. A.lower characteristic impedance is possible. The model is analysed, applying Lienard's graphical method and linear approximations. As a result the criteria for characteristic parameters of negative resistance elements to operate as a neuristor are obtained. Based on the results, a neuristor with low inductance, small power, and high-speed operation can be designed. This circuit is convenient for neuristor logic, because, compared with the peculiar pulse width, it has a long delay time per section. The paper also describes neuristor logic without an R-type junction, using only the threshold property of the neuristor. A conventional Crane's R-junction is also presented. For this neuristor model a destructive collision phenomenon exists independent of the refractory period phenomena. The mechanisms of these phenomena are clarified.