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In order to predict the surface topography, a chip-scale oxide chemical mechanical planarization (CMP) model is proposed in poly opening polishing processing of high-k metal gate (HKMG) structures. A geometrical chemical vapor deposition model is first constructed to describe the influence of design pattern effects on the initial surface profiles of dielectric oxides. Based on contact mechanics, the global pressure distribution is then computed to incorporate the long-range features of design structures and polishing pad deformation. The global pressure is further combined with local pattern effects to construct a feature-scale material removal rate model, which can be utilized for surface topography simulation of design chips. The predicted results of the proposed CMP model are consistent with the experimental data collected from the test patterns of HKMG CMP process. Consequently, the oxide CMP model has good potentials of predicting the surface planarity of polishing wafers and optimizing some design rules for HKMG design layouts.
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Chen et al. (2018) studied this question.
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