Short-channel vertical sidewall MOSFETs

Vertical MOSFETs have been proposed in the roadmap of semiconductors as a candidate for sub-100-nm CMOS technologies. In this paper, vertical n-channel MOSFETs with channel length down to 50 nm are presented, fabricated in a standard production line with i-line lithography. A process flow using side wall gates and implantations instead of multiple layer depositions reduces process complexity and offers better CMOS compatibility. With this particular vertical MOSFET structure, called the vertical sidewall MOSFET, high doping concentrations in the channel are needed for sub-100-nm devices. The uniform channel doping is more critical for vertical transistors than for a planar technology, where optimized profiles can be easier implemented. Therefore, we investigated vertical MOSFETs with high channel doping concentration up to 1/spl times/10/sup 19/ cm/sup -3/ and channel lengths down to 50 nm. The impact of the high doping levels on threshold voltage and on tunneling currents is discussed. Finally, by using slight process modifications first results on vertical double-gate MOSFETs will be presented, which in principle can operate with an undoped channel region.