A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors

Novel capacitive fingerprint sensor techniques are described. We propose a novel sensor cell architecture to obtain high sensitivity, wide output dynamic range, and contrast adjustment. For the architecture, three circuit techniques were developed. A sensing circuit with a differential charge-transfer amplifier enhances sensitivity while it suppresses the influence of the parasitic capacitance of the sensor plate. A wide output dynamic range, which is needed for high-resolution analog-to-digital (A/D) conversion, is achieved by transforming the sensed voltage to a time-variant signal. Finally, the sensing circuit includes an automatic contrast enhancement scheme that uses a variable-threshold Schmitt trigger circuit to distinguish the ridges and valleys of a fingerprint well. The characteristics of a test chip using the 0.5-/spl mu/m CMOS process show a high sensitivity to less than 80 fF as the detected signal, while the variation of the output signal is suppressed to less than 3% at /spl plusmn/20% variation of the parasitic capacitance. The dynamic range of the time-variant signal is 70 /spl mu/s, which is wide enough for A/D conversion. The automatic contrast enhancement scheme widens the time-variant signal 100 /spl mu/s more. A single-chip fingerprint sensor/identifier LSI using the proposed sensing circuit scheme confirms the scheme's effectiveness.