Answers are grounded in this paper and cite their sources.
A mixed-signal RAM decision-feedback equalizer (DFE) that operates at 90 Mb/s is described. In the analog domain, the DFE subtracts intersymbol interference caused by the past four outputs. The equalized signal is fed into a nonuniform flash analog-to-digital converter (ADC) to produce the decision output and error signal used to adapt the RAM contents in the digital domain. With a 5 V supply voltage, the power dissipation is 260 mW during steady-state operation. The active area is 4.5 mm/sup 2/ in a 1 /spl mu/m CMOS process.
No takes yet. Share an insight, caveat, or question.
Rothenberg et al. (1997) studied this question.
Synapse has enriched 10 related papers. Consider them for comparative context: