Modeling of Cu-CMP and Its Application for Hotspot Prediction

In sub-100 nm nodes, continuously shrinking CD imposes more demanding requirement on wafer planarity to satisfy constrains of diminishing DOF of lithography process. However, due to incoming non-planarity of wafer surface caused by ECP, and inherent removal rate selectivity regarding to dielectric and metal films of CMP slurries, post Cu-CMP topography exhibits strong dependency not only on process conditions, but also on layout pattern of processed wafers. In this paper, such layout pattern-dependency of post Cu-CMP topography was studied with a pre-designed test chip. Post CMP Cu line thickness and area array-height were characterized with respect to metal line width and feature pattern density. Semi-empirical models were built based on multivariate response surface methodology (RSM) to simulate post Cu-CMP surface topography. By applying the developed models, post CMP Cu-line thickness and area array height were predicted across a shot of M1 layer of a typical 40 nm logic product. The prediction is verified by TEM cross section for selected features. Potential risky hotspots were successfully highlighted by the models.