A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer

A dual 10-b/200-MSPS pipelined digital-to-analog converter (DAC) suitable for communication applications is here presented. Prior implementation limitations have been overcome through circuit techniques. A prototype has been designed using a 4-metal-levels 3.3-V 0.5-/spl mu/m BiCMOS technology and operates on a 3-phase clock synthesized by an on-chip delay-locked loop (DLL). The DAC shows 9.7 effective bits and 70 dB of spurious free dynamic range for a synthesized sine wave of 2 V/sub pp/ at 34 MHz and output rate of 200 MSPS. Altogether, the two DACs, their reference, and the DLL occupy an active area of 2.28 mm/sup 2/ and consume 693 mW at full speed.