Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices

A numerical model for obtaining linear doping profiles in the drift region of high-voltage thin-film SOI devices is proposed and experimentally verified. Breakdown voltage in excess of 612 V on LDMOS transistors with 0.15-/spl mu/m SOI layer, 2-/spl mu/m buried oxide, and 50-/spl mu/m drift region is designed and demonstrated using this model. Theoretical and experimental dependence of the breakdown voltage on the drift region length are compared. Good agreement between the simulation and experimental results are obtained. Dependence of the breakdown voltage on the doping density and doping concentration slope in the linearly doped drift region is also investigated experimentally. Results indicate that an optimum concentration slope is needed in order to optimize the breakdown voltage in the thin-film SOI devices with a linear doping drift region. Finally, a 600-V CMOS compatible thin-film SOI LDMOS process is also described.