LFSR-Based Error-Resilient Ternary Content-Addressable Memory for High-Speed Fault-Tolerant Data Storage and Search

Content-addressable memories provide fast parallel lookup but remain vulnerable to storage faults, synchronization errors, and implementation overhead when realized using SRAM-based structures. This work presents an Error-Resilient Ternary Content-Addressable Memory (ER-TCAM) that incorporates Linear Feedback Shift Registers (LFSRs) for randomized address generation and synchronized memory access. The proposed architecture combines LFSR-based storage, an address generation unit, a read/write controller, bit-wise error detection, and an Error Correction Vector (ECV) computation unit. The error-detection path generates an encoded indication of the faulty LFSR word, while the correction path reconstructs and rewrites the corresponding error-correction information without preventing lookup activity. The design was modeled in Verilog and implemented using Xilinx ISE 14.2. The supplied synthesis results report 32 slice registers, 128 LUTs, 16 fully used LUT-FF pairs, a delay of 0.316 ns, and power consumption of 0.042 W. The reported simulation also demonstrates recovery of an error-corrupted stored value to the correct output. Comparative results against DyTAN, MTCAM, and CN-TCAM show lower resource use, delay, and power for the proposed ER-TCAM.