A 113.7 dB SINAD, 18.59 Bit ΣΔ Modulator for High-Resolution ECG Recordings

High-Resolution Electrocardiograms (HRECGs) are essential to detect low-amplitude signals in the ventricles known as "Late Potentials" that cannot be detected with a standard ECG. This work presents the design of a fully-differential second-order Cascade-of-Integrators with Feedforward (CIFF) one-bit Continuous-Time (CT) ΣΔ modulator for HRECG recordings. The modulator incorporates two active RC loop filters, a summer, and a StrongARM latch, along with a single-bit resistive DAC. Integrator and summer circuits are designed using a differential operational transconductance amplifier (DOTA). The area of the pMOS input transistors in the first-stage integrator is increased compared to that of the second-stage integrator and summer to reduce flicker noise. The StrongARM latch is implemented without using a preamplifier, leading to a reduction in area and power dissipation. The designed ΣΔ Modulator (ΣΔΜ) circuit achieves a high Signal-to-Noise And Distortion ratio (SINAD) and resolution through an optimal design approach and a higher oversampling ratio (OSR). The proposed ΣΔM architecture is implemented using the MATLAB delta-sigma toolbox at the system-level and the Cadence Virtuoso EDA tool at 0.18µm CMOS technology at the circuit-level. The simulated performance parameters are validated at behavioral, macromodel, and circuit levels. To measure ECG signals of 150Hz bandwidth, a 300 kHz sampling frequency ( ) is used, resulting in an OSR of 1000. The proposed design achieves a SINAD of 113.7dB and a resolution of 18.59 bits. The modulator's measured power consumption is 0.49mW, achieving Schreier's Figure-of-Merit (FoM) of 168.55 dB, occupying an active area of 0.582 mm2.