RF Characterization of Vertical Wrap-Gated InAs/High-κ Nanowire Capacitors

This paper presents RF as well as low-frequency capacitance-voltage (C-V) characterization of vertical wrap-gated InAs/high-κ nanowire MOS capacitors. A full equivalent circuit model for traps is used to fit the low-frequency C-V characteristics, from which the interface trap density (Dit) and border trap density (Nbt) are evaluated separately. The results show comparable Nbtbut far lower Dit(12eV-1cm-2near the conduction band edge) for a nanowire MOS gate-stack compared with planar references. In the RF domain, the influence of nanowire series resistances become significant, and by introducing a distributed RC-model, the nanowire resistivity (ρnw) is evaluated from the capacitance data as a function of the gate bias. An ON/OFF ρnwratio of 10-2is obtained for the best device. Using the measured data, the quality factor is finally evaluated both for fabricated and ideal capacitors. The results agree well with simulated data.