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February 25, 2015Japanese Journal of Applied Physics

Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs

Jae-Ho Hong Sanghyun Lee Ye-Ram Kim Eui-Young Jeong Jun-Sik Yoon Jeong‐Soo Lee Rock‐Hyun Baek Yoon‐Ha Jeong

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Abstract

Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs, Hong, Jae-Ho, Lee, Sang-Hyun, Kim, Ye-Ram, Jeong, Eui-Young, Yoon, Jun-Sik, Lee, Jeong-Soo, Baek, Rock-Hyun, Jeong, Yoon-Ha

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Cite This Study

Hong et al. (2015) studied this question.

synapsesocial.com/papers/6ab1e3bf226074e4f918e7b9 https://doi.org/10.7567/jjap.54.04dn05

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