Bitline GND sensing technique for low-voltage operation FeRAM

This is the authors' abstract. We don't add key points for this paper.

In this sensing technique, pMOS charge transfer maintains the bitline level near the GND when the plate line goes high. It gives 0.5-V higher readout voltages across the cell capacitors and enables a 0.4-V higher differential amplitude in a 512-cell per bitline structure compared with the conventional high-impedance bitline sensing technique. Using the shifted bias plate line layout, only eight cells and eight sense amplifiers per cell mat are activated, and simulations show 8.06 mW at 3 V and 5 MHz, which is about the same power consumption as the conventional device.