Scalable Electrical Compact Modeling for Graphene FET Transistors

A new scalable electrical compact model for the Graphene FET devices is proposed. Starting from Thiele's quasianalytical model, the equations are modified to be fully compatible with SPICE-like circuit simulation. Compared to Meric et al. model, the charge model is improved. This large signal model has been implemented in Verilog-A code and can be used for simulation in a standard circuit design environment such as Cadence or ADS. This model has been verified using different measurements from the literature, and furthermore, its scalability is demonstrated.