Simulation and experimental study on a high figure of merit LDMOS with ingenious layout design

This is the authors' abstract. We don't add key points for this paper.

To improve the tradeoff relationship between the specific on-resistance (R on,sp) and breakdown voltage (BV), a novel lateral double-diffusion metal-oxide-semiconductor field effect transistor (LDMOSFET) with an ingenious layout design is proposed and investigated by simulations and experiments. The proposed LDMOS features a specific convex-shape field plate (CFP) structure at source side and two separated integrated diodes (SID) at the drain side. On one hand, a continuous electron accumulation layer is formed from source to drain in the on-state, providing an ultralow current path to decrease the R on,sp. On the other hand, the CFP and SID structures allow the proposed device to make full use of the drift length to sustain the off-state voltage, so that the novel device could maintain the same BV level with a shortened drift length. Thus, the proposed CFP–SID LDMOS achieves a much lower R on,sp and better R on,sp–BV tradeoff relationship. The experimental results illustrate that the CFP–SID LDMOS realizes a BV of 518 V and R on,sp of 23.5 mΩ·cm2 with a high figure of merit (FOM) of 11.42 MW cm−2. Compared with the triple-RESURF LDMOS under the same BV, the proposed device decreases the R on,sp by 53.8%.