A High‐Linearity, Wideband Source Follower Using Dual‐Band Compensation in 5‐nm FinFET

A low‐power, high‐linearity input buffer for multi‐GS/s analogue‐to‐digital converters is presented. A third‐order Volterra‐series model is utilised to characterise a source follower biased near the saturation–triode boundary, revealing the interaction between static resistive and dynamic capacitive nonlinearities. Based on this analysis, a dual‐band compensation topology employing parallel auxiliary differential pairs is designed to mitigate these distortions, enabling a lower core supply to save power. As a pre‐silicon design study, the proposed buffer is validated through transistor‐level simulations using a 5‐nm FinFET PDK, achieving an SFDR of 81 dBc at 0.95 GHz and 65 dBc at 10.2 GHz for a 0.8‐V pp differential swing, while consuming 48 mW from 1.2‐V and 1.5‐V supplies.