Reconfigurable Logic Operation of MoTe 2 Homojunction Enabled by Staggered Double‐Sided Contacts

Reconfigurable transistors capable of dynamically switching between p‐ and n‐type operations are highly desirable for compact and energy‐efficient logic circuits. Here, we demonstrate a reconfigurable MoTe 2 transistor enabled by a staggered double‐sided contact (SDC) architecture, where a nanoscale gap adjacent to one electrode preserves the intrinsic state of the channel and creates a wide carrier barrier. Gate voltage modulates the channel into either a p‐i or n‐i homojunction, yielding unipolar p‐type or n‐type behavior depending on the bias. This polarity reconfiguration is ensured when the absolute bias voltage is less than the gate voltage, and the device achieves a high on/off ratio of 10 6 and a near‐ideal subthreshold swing of 67.6 mV/dec. Polarity reconfiguration is realized in both top‐gate and bottom‐gate configurations. Using the top‐gate SDC transistor, we construct p‑metal‑oxide‑semiconductor, n‑metal‑oxide‑semiconductor, and complementary metal‐oxide‐semiconductor inverters with a maximum gain of ∼28 and a minimum static power consumption as low as ∼1 nW. The simple electrode design, combined with high performance and logic versatility, positions the MoTe 2 SDC transistor as a promising building block for future high‐integration low‐power reconfigurable logic systems.