Bidirectional Peripheral Nerve Interface With 64 Second-Order Opamp-Less ΔΣ ADCs and Fully Integrated Wireless Power/Data Transmission

This is the authors' abstract. We don't add key points for this paper.

An active probe and microstimulator SoC for interfacing with peripheral nerves is presented. It performs 64-channel artifact-tolerant neural recording, cuff imbalance compensation by impedance sensing, and neurostimulation for the closed-loop operation. Each recording channel is a second-order opamp-lessΔ ΣADC that consumes 140 nW and occupies 0.01 mm2area in 130 nm CMOS. The single-loopΔ Σarchitecture achieves second-order noise shaping with two passive integrators. To the best of our knowledge, this yields the lowest power and area of any second-orderΔ ΣADC and the lowest FOM (fJ/conv. step) of any passive second-orderΔ ΣADC (27 fJ/conv. step). The SoC uniquely performs multi-modal input signal recording: voltage (for neural recording) and current (for impedance sensing) are measured concurrently using frequency multiplexing. The SoC also features a 60 MHz energy-efficient inductive powering link and a 600 MHz RF data communication link. The prototype is validatedin vivoin the rat sciatic nerve for electroneurogram (ENG) sensing and the correction of impedance-imbalance in cuff electrodes.