The demand for high-throughput, multi-modal recording and stimulation in neuroscience research has driven the development of neural interfaces that optimize area and energy efficiency without compromising noise performance. Simultaneously, the need for on-chip data compression to reduce data volume has become increasingly critical. This work presents a neural interface system-on-chip (NISoC) that incorporates 1,024 channels for simultaneous electrical recording and stimulation, enabling high-resolution, high-throughput electrophysiology with record noise-energy efficiency. The 2 mm × 2 mm NISoC, fabricated using 65 nm CMOS technology, integrates a 32 × 32 array of electrodes vertically coupled to analog front-ends. These front-ends support both voltage and current clamping through a programmable interface, providing a voltage range up to 100 dB and a current range of 120 dB. Each channel operates at a power consumption of 0.81 µW, achieving an input-referred voltage noise of 8.8 µVrms over a signal bandwidth from DC to 12.5 kHz. The NISoC also integrates on-chip data acquisition through a back-end array of 32 dynamic incremental SAR ADCs, achieving 25 Msps and 11 effective number of bits (ENOB) acquisition with an energy efficiency of 2 fJ/level. The dynamic incremental SAR ADC architecture further offers additional functionality of intrinsic spike detection for future on-chip neural data compression.
Wang et al. (Wed,) studied this question.