An 112-Ch Neural Signal Acquisition SoC With Full-Channel Read-Out and Processing Accelerators

Multichannel neural signal acquisition and processing play a pivotal role in advancing neuroscience research. This article proposes a 112-channel system-on-chip (SoC) design for neural signal acquisition and processing, comprising full-channel read-out circuits, neural signal-processing accelerators, and a 32-bit RISC-V core. A clock-domain-crossing (CDC) structure is devised to minimize data storage overhead in read-out circuits, facilitating comprehensive data acquisition and high-throughput simultaneous transmission from all channels. The channel-specific processing unit incorporates hardware-efficient designs for lossless compression, spike detection, and extraction of spike features. A multistage predictor module serves the dual purpose of narrowing data distribution during compression and signal augmentation during spike detection. The proposed design was fabricated in 40-nm technology with an area of 6.67 mm <tex-math notation="LaTeX">²</tex-math> . The acquisition of 112 channels achieves a peak data rate of 57.3 Mbps, with a total power consumption of 3.07 mW, wherein 0.87 mW is attributed to the read-out circuits. The processing accelerators feature an area consumption of 0.011 mm <tex-math notation="LaTeX">²</tex-math> /ch, and a minimal power consumption of only 0.2 <tex-math notation="LaTeX">~μ</tex-math> W/ch under a 32-kHz clock. The effectiveness of the proposed design is validated through in vivo recording experiments conducted on rats by integrating with flexible implantable electrodes.