20–40 GHz dual‐gate frequency doubler using 0.5 μm GaAs pHEMT technology

A Ka‐band dual‐gate frequency doubler using 0.5 μm GaAs enhancement‐mode pHEMT process is presented. The cascode circuit is equalised to the dual‐gate frequency doubler and the relationship between bias and output matching is discussed to obtain the maximum output power and conversion efficiency. Since a pinch‐off gate‐to‐source bias is driven at the input gate node, the frequency doubler consumes little DC power when injecting a low‐power fundamental signal. Based on the analysis, the designed dual‐gate doubler has a 3 dB bandwidth of 5.6 GHz, from 36 to 41.6 GHz. The fundamental suppressions are better than 15 dB. The measured maximum conversion gain is −0.9 dB at an injected power of 7 dBm. A high saturation output power is 7 dBm with a conversion efficiency of 14.3%. The measured results confirm the validity of the proposed analysis method.