Optimizing Set Performance for Phase Change Memory with Dual Pulses Set Method

Applying a high power pulse (HPP) before the standard single box SET pulse accelerates the crystallization process and reduces the SET resistance of phase change memory (PCM) cells. The effects of HPP on SET resistance distribution are characterized and analyzed. Dual pulses SET method (D-SET) is proposed and compared with some conventional SET methods. The results gathered across a 16 Kbits block of a 64 Mbits PCM test chip in 40 nm CMOS process show that D-SET achieves the fastest SET speed, the narrowest SET resistance distribution and smallest drift coefficient with set time of 300 ns.