On a dual-polarity on-chip electrostatic discharge protection structure

A novel dual-polarity on-chip electrostatic discharge (ESD) protection structure is designed. The new ESD structure protects IC chips against ESD stressing in the two opposite directions. The ESD structure features symmetric deep-snapback current-voltage (I-V) characteristics, low-impedance active overcurrent discharging path, low holding voltage for overvoltage clamping, fast ESD response of /spl sim/0.18 ns, low leakage (/spl sim/pA), adjustable triggering voltage, and good scalability. It passes 14 KV HBM ESD zapping tests and achieves high ESD-performance-to-Si ratio of /spl sim/80 V//spl mu/m width. The new ESD structure reduces Si areas consumed by ESD protection units and ESD-induced parasitic effects significantly.