Topology optimization of heat sinks for multi-chip systems considering thermal interaction and load imbalance

The increasing power density of multi-chip electronic systems poses thermal-management challenges associated with localized hotspots, unequal chip loading, and inter-chip thermal coupling. Existing topology-optimization studies for electronic cooling have largely focused on single heat sources or individual operating conditions, while thermal interaction between multiple chips under varying power combinations has received less attention. This study develops a multi-load topology-optimization approach for a dual-chip heat sink under steady-state heat conduction. Nine representative load cases are defined within prescribed chip-power ranges, and the objective function penalizes junction-temperature exceedance and inter-chip temperature imbalance across these cases. After optimization, the resulting heat sink is treated as a fixed thermal system and characterized using an effective junction-to-ambient thermal-resistance matrix identified from two single-source simulations and cross-validated against mixed-load cases not used for matrix identification. Compared with the baseline heat sink, the optimized design reduces the self-heating resistances of Chips 1 and 2 by 73.8% and 73.4%, respectively, and the mutual coupling resistances by approximately 66.6%. For the operating-envelope analysis, with the ambient temperature T a = 293.15 K and the prescribed junction temperature limit T lim = 330 K, restricting the thermally feasible region to P 1,max = 45 W and P 2,max = 65 W yields a bounded feasible operating area that increases from 283.32 to 2638.04 W 2 , corresponding to an increase of 831.12%. The unit W 2 denotes the area of the admissible region in the two-dimensional P 1 − P 2 power space rather than a physical geometric area. These results show that multi-load topology optimization can redistribute conductive heat-transfer paths, reduce both self-heating and inter-chip thermal interaction, and substantially extend the admissible operating range of dual-chip thermal systems.