Design of a High Speed Bit-Length Independent FinFET Based Hybrid Carry Look Ahead-Carry Skip Adder for Future Signal Processing Systems

In this work, an energy efficient and high speed 16 nm FinFET based hybrid wider bit-length CLACS-adder that combines CMOS-domino structure based 8-bit MCC-adder module and Concatenation & incrementation techniques-based carry-skip module implemented in wide V DD -levels. The carry outputs of the proposed hybrid adder are obtained in parallel by adopting two separate FinFET based 4-bit even & odd MCC-chains. Concatenation & incrementation blocks are additionally used to boost the speed of the innovative wide bit-length hybrid CLA-CS-adder. Finally, the new hybrid CLA-CS wide bit-length adder uses AOI (AND-OR-Invert) and OAI (OR-AND-Invert) logic-gates for the carry-skip logic circuit instead of multiplexer-logic. The 16nm FinFET-based adder with 8-,16-,32- and 64-bit sizes implemented with V DD = 0.7 V offered a τ PD of 60.39/79.87 pS, 98.7/123.5 pS, 101.1/124.1 pS and 103.8/124.1 pS, respectively and these hybrid CLA-CS wider bit size adders showcased a P Dynamic of 188.1/148.5 μW, 418.6/333.5 μW, 850.4/674 μW, and 1680/1350 μW, respectively, at 27°C/107°C. When the bit-length is 16 or more the proposed adder shows approximately similar delays which indicate the size-independent speed performance of the new design. The new energy efficient and high-speed wider bit size FinFET-based hybrid adders are highly suitable for future signal-processing systems and IoT applications.