12T-SLCAFA: Novel Design of a Stacked Leakage Control Approximate Full Adder Featuring Twelve 32 nm CNTFET Devices for Image Sharpening Application

The error-tolerance ability of certain computing applications, such as image processing, is being leveraged by many contemporary researchers in achieving logic simplification to reduce power consumption and propagation delay in digital circuits at the expense of introducing a few errors. In this work, a novel design of an approximate full adder (AFA), which is a building block of digital processors, has been reported using twelve 32 nm CNTFET transistors. A combination of approximate mirror adder and gate diffusion input techniques has been utilized to design the AFA that also features a novel implementation of a stacked leakage control (SLC) transistors-based inverter. Abbreviated as 12T-SLCAFA, its dynamic power dissipation of 3.241 nW is 1.17 to 2.35 times lower than the contemporary designs at an operating voltage of 0.5V. At the same operating conditions, its average propagation delay of 3.7825 ps is up to 2.3 times lower than the contemporary approximate adder circuits. Furthermore, an approximate ripple carry adder has been designed for higher-order implementation and image sharpening, yielding promising results, including a peak signal-to-noise ratio of 29.88 dB and a structural similarity index of 0.91, making the proposed design ideal for image processing applications.