A small-area and power-efficient reversible full adder based on a two-transistor multiplexer applicable in image addition

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This study presents an innovative 10-transistor reversible full adder (FA) architecture featuring two garbage outputs (GOs) and no constant inputs (CIs). The design integrates three reversible logic gates across two operational stages, implemented using the gate diffusion input (GDI) methodology. Specifically, it employs two Feynman gates alongside a newly developed GDI-based reversible multiplexer (R-MUX-GDI) to produce the Sum and Carry-out (C out ) signals. The 3 × 3 multiplexer, with two GOs and only two transistors, substantially minimizes the circuit’s footprint. The input configuration is strategically designed to limit excessive GOs. When incorporated into a ripple carry adder (RCA) for image processing, the proposed FA demonstrates exceptional performance in terms of area efficiency, power consumption, and output image quality. Simulations conducted using 32 nm carbon nanotube field-effect transistor (CNTFET) technology at a 0.9 V supply voltage (V DD ) reveal that the proposed circuit achieves a power consumption of 1.0388 µW, which is minimal compared to its counterpart. The power delay product (PDP) of the FA is 6.744 aJ, which makes it a candidate for low-power reversible computing and room-temperature quantum-adjacent control circuitry. Furthermore, implementing the FA in 4-bit, 8-bit, 16-bit, and 32-bit ripple carry adder (RCA) configurations requires 48, 96, 192, and 384 transistors, respectively, underscoring its substantial area savings and effective image processing capabilities.