A Multi-Chip Cascadable MIC6_V4 ASIC for the NICA-MPD Inner Tracking System

To meet the upgrade requirements for the Inner Tracking System (ITS) of the Multi-Purpose Detector (MPD) at the Nuclotron-based Ion Collider facility (NICA) for extremely high spatial resolution and low material budget, we present a monolithic active pixel sensor array chip, MIC6 V4, using GSMC 130 nm CMOS process. The chip features a pixel array size of 497 rows by 980 columns, with individual pixels measuring 30.53 μm × 26.8 μm, and the overall die area of 30mm × 15 mm. The MIC6_V4 chip communicates with external readout electronics through a high-speed data output interface with a maximum data rate of 1.2Gb/s, and also supports data transfer between chips via a bidirectional parallel bus with a clock frequency of 40 MHz. This paper primarily describes the digital peripheral design and implementation of the MIC6_V4 chip, presenting a digital readout architecture that accommodates varying pixel hit rates within the Inner Tracking System (ITS) and supports both single-chip standalone operation and multi-chip interconnection.