3D integration of 2D electronics for AI hardware

This is the authors' abstract. We don't add key points for this paper.

The relentless demand for faster, smaller and more energy‐efficient integrated circuits has pushed the semiconductor industry to the performance, power and area (PPA) wall, where interconnect delay and energy dissipation dominate system efficiency. While 2.5D and TSV‐based 3D integration offer partial relief, they suffer from long interconnects, thermal hotspots and reliability concerns. Monolithic 3D integration (M3DI) provides a transformative TSV‐free paradigm, enabling nanoscale vertical interconnects between front‐end‐of‐line logic and back‐end‐of‐line memory tiers, thereby maximizing PPA efficiency and reducing latency. Here we demonstrate M3DI of two‐dimensional (2D) electronics, integrating single‐crystalline MoS 2 field‐effect transistors with nanocrystalline WS 2 memristors in a vertically stacked 1T1R architecture. These atomically thin devices are BEOL‐compatible and scalable, offering uniform threshold and Ion/Ioff distributions for logic, and stable filamentary switching with narrow SET/RESET variability for memory. The resulting arrays achieve ultra‐dense integration, reproducible operation and low‐latency performance within a compact footprint. Beyond binary switching, the M3DI‐1T1R chip exhibits synaptic functionalities including multistate non‐volatile memory, spike‐timing‐dependent plasticity and array‐level uniformity, essential for neuromorphic and AI hardware. This work establishes 2D‐material‐based M3DI as a compelling foundation for next‐generation intelligent and energy‐efficient computing systems beyond CMOS scaling and von Neumann architectures.