Gate-level three-dimensional integration of two-dimensional logic cells

Monolithic three-dimensional (M3D) integration is a promising strategy to increase logic density within a limited footprint. Conventional M3D circuits rely on transistor-level partitioning, in which logic functions are constructed through interconnections among numerous transistors across different tiers, limiting circuit compactness. Here, we propose a gate-level M3D integration architecture based on two-dimensional (2D) logic cells (LCs), in which the basic interlayer connection unit is shifted from an individual transistor to a logic gate. Through multidimensional modulation of carrier transport in the WSe2 channel, LCs can realize eight distinct logic functions, markedly expanding the functional reconfigurability of 2D logic devices. Building on this architecture, we experimentally demonstrate stacking of two-tier LCs, realizing complex 3D logic circuits with unprecedented compactness. Across all demonstrated logic functions, only 4 devices are required, whereas a conventional CMOS design would require 79 transistors. This gate-level M3D integration provides a scalable pathway for constructing highly compact and multifunctional electronics. Monolithic three-dimensional integration can raise logic density, but transistor-level connections limit circuit compactness. Zhao et al stacked reconfigurable two-dimensional logic cells at the gate level, creating complex circuits with markedly fewer devices.