The hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Upon hot-carrier stress, two different, and competing degradation mechanisms are present: channel electron mobility reduction due to interface trap formation, and injection and trapping of hot holes in the accumulation region of the transistor. It will be shown that the latter mechanism is absent in the vertical DMOS.
No takes yet. Share an insight, caveat, or question.
Moens et al. (2004) studied this question.
Synapse has enriched 2 closely related papers on similar clinical questions. Consider them for comparative context: