Tuning Avalanche Path in Vertical GaN JFETs By Gate Driver Design

The 1.2-kV vertical gallium nitride (GaN) fin-channel junction-gate field-effect transistor (JFET) has recently emerged as a promising candidate for power electronics. It is normallyoffand has a specificon-resistance smaller than that of 1.2-kV SiCmosfets. A robust avalanche capability has also been reported in vertical GaN JFETs with an avalanche current flowing through the gate. This avalanche path differs from that of powermosfets(via the source) and may pose challenges in gate driver reliability. This article, for the first time, demonstrates that the avalanche current in GaN JFETs can be tuned to flow through the source, by using either amosfetdriver with a large gate resistance or anRC-interface driver. These drivers turnonthe fin channel during the device avalanche and obviate a large avalanche current into the gate driver. The carrier dynamics within the GaN JFET under the two avalanche paths have been unveiled by physics-based mixed-mode electrothermal simulations. The critical avalanche energy density in both paths was found to be comparable with the state-of-the-art SiCmosfets. Additionally, theRC-interface driver was shown to outperform themosfetdriver for vertical GaN JFETs. The learning about normallyoffGaN JFETs was applied to a study of commercial normallyonSiC JFETs. Two avalanche paths of a similar nature were observed with different gate drivers. This article provides new insights of the JFET avalanche and show the excellent robustness of the novel 1.2 kV vertical GaN JFET.