Parity-preserving reversible sequential logic for quantum systems: Miller synthesis, NCV mapping, and IBM quantum validation

Modern computing relies on very-large-scale integration (VLSI)-integrated systems for higher-dense, high-speed integration of complex digital subsystems with more energy-efficient, reliable, and compact systems. Quantum systems are emerging technologies supporting next-generation computing workloads through quantum/reversible gates. Sequential design synthesis with optimized parameters has been explored in the era of quantum technology. A reversible/quantum design flow requires optimized building blocks for storage and control to enable efficient integration and reuse of systems. A parity-preserving reversible sequential circuit is attractive for integrated quantum/reversible platforms because it embeds a low energy dissipation, inherent error-indication property, while maintaining unique input reconstruction capability. We propose a compact 5 × 5 parity-preserving reversible D-gate as a core design for reusable sequential circuit designs. A transformation-based Miller synthesis is used to structure the novel D-gate, which is then mapped to the NCV library and optimized via simplification/templates, which reduces the quantum cost (QC) to 7 (58.82%). The D-gate is used to synthesize low-overhead D-FFs, counters, and shift registers. The proposed D-FF designs achieve QC = 7, garbage output (GO) = 2, constant input (CI) = 2, and gate count (GC) = 1. These values match the lowest QC reported among the selected D-FF baselines while reducing GO, CI, and GC relative to several prior designs. Compared with the best previous one, the proposed designs reduce QC by 22.22%, GO by 33.33%, CI by 33.33%, and GC by 50.00%. Further design of various circuits, such as up/down counters, Johnson counters, and shift-register families are developed. The proposed SIPO design achieves QC = 28, GO = 6, CI = 8, and GC = 4, reducing QC by 41.67%, GO by 40.00%, and GC by 50.00% compared with the representative prior shift register, while CI remains unchanged. We use IBM-Qiskit quantum simulation to validate qubits in the D-FF design. Furthermore, a noise-aware D-FF simulation is performed in the IBM-Qiskit environment to examine the behavior of the proposed circuit under selected quantum noise models. As a result, proposed parity-preserving sequential blocks can be used as elements for quantum and reversible computing platforms integrated into complex systems.