Competing hysteresis mechanisms in HZO/MoS2 transistors with a metal–ferroelectric–metal–insulator–semiconductor gate stack

Ferroelectric field-effect transistors based on hafnium oxide offer a versatile platform for advanced memory concepts. Here, we demonstrate a proof-of-concept top-gated Hf0.5Zr0.5O2-based transistor integrating a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) gate stack with a two-dimensional MoS2 channel. The implementation of such an architecture is particularly challenging in MoS2, where the strong sensitivity of the channel to trapped charge can further complicate the balance between ferroelectric switching and charge redistribution within the MFMIS stack. By varying the MFM-to-MIS area ratio and the applied gate-voltage amplitude, we observe a systematic evolution of the transfer hysteresis consistent with competing ferroelectric polarization switching and trap-related contributions. Temperature-dependent measurements, zero-bias write/read experiments, and compact Simulation Program with Integrated Circuit Emphasis modeling provide additional support for this interpretation. Despite the non-optimized gate stack, a substantial ferroelectric contribution to the device response is retained, while retention measurements reveal limitations associated with depolarization and trapping. These results demonstrate the feasibility of MFMIS ferroelectric transistors based on MoS2 and provide a basis for further optimization of their gate-stack design and memory performance.